1. Field of the Invention
The invention relates in general to a method of fabricating a protection structure. More particularly, the invention relates to a method of fabricating a protection structure which can be used to protect both a PMOS and an NMOS.
2. Description of the Related Art
In an integrated circuit, after the formation of certain devices, there are still some processes to be performed to complete the circuit layout. For example, after a PMOS or an NMOS is formed on a substrate, to obtain an electrical connection between PMOS or NMOS and other devices or terminals, a conductive layer is formed and patterned. While patterning the conductive layer, an etching step is inevitable. The plasma or other charged particles used to etch the conductive layer very often damage the NMOS or PMOS formed on the substrate. To protect the PMOS or NMOS from being damaged by the accumulated charged particles or carriers, a protection diode (PD) is formed in prior fabrication technology. Typically, for an NMOS, an N+/P- diode is formed to direct negative charges to the ground. In contrast, for a PMOS, a P+/N- diode is formed to dissipate the positive charges.
FIG. 1A and FIG. 1B respectively show circuit diagrams of protection diodes used for NMOS and PMOS. As shown in the figures, since the polarity of protection diodes required by the NMOS and the PMOS are different, if one is to fabricate a single protection diode in one substrate having both PMOS and NMOS, the conventional technique cannot achieve the objective.
Furthermore, after the formation of the devices in and on the substrate, a multi-level interconnect is typically formed on the devices to complete the circuit layout. The electrical connection between the gate and the protection diode very often degrades the performance and electrical characteristics of the circuit.